There are strong needs for downsizing, weight reduction and functional upgrading in the recent fields of mobile devices, such as cellular telephones, personal audio players, hand held navigation devices, and information/home appliances, which eventually demands functional upgrading of LSI (large-scale integrated circuit). Thus there is an accelerated trend of fabricating circuits using a plurality of different processes on a single wafer, which is known as SOC (system-on-chip). SOC, however, requires a longer and more complicated process as compared with a single process, and thus has general tendencies of lower yield ratio and longer development period. SOC is also disadvantageous in that the individual circuits cannot be fabricated according to respective optimum processes since all processes are carried out on the wafer basis, which may yield poorer functions ones rather than those obtained in the single process.
In recent years, interest has been growing in the area of a system-in-package (SIP). The SIP enables the same kind of or different kinds of LSI or IC, to be fabricated by the conventional single process. The individual IC's may be inspected as non-defective and assembled into a unit or module which can be handled as a single component (LSI or IC) by combining and re-wiring. SIP can thus readily realize an LSI unit or IC package having a high yield ratio and diversified functions.
A common requirement of all SIP devices is the incorporation of discrete passive devices with the multiple integrated circuits that make-up the system. In some cases resistors might be used for level translation between two different semiconductor technologies that must be combined in the same package. The power systems of all SIP devices need capacitors or inductors for conditioning and isolating the power source. These devices are normally mounted on a substrate that provides a conductive path that terminates adjacent to the destination IC. A bonding wire is normally used to complete the connection path.
Many of today's high speed devices require tight impedance control on the interconnection path. This presents a serious problem to the signal quality of the normal interconnect solution. As the number of high speed interconnections increases, the integrated circuit dice are pushed closer together in order to reduce the effects of the conductive path between the dice. These conflicting requirements may cause delay in system delivery in order to reconfigure the dice or increase the size of the package in order to accommodate a large number of interconnect structures adjacent to the dice.
Thus, a need still remains for an integrated circuit packaging system with passive components, that satisfies the signal quality needs without increasing the size of the SIP. In view of the increasing demand for more function packaged in smaller spaces, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.